1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to methods of removing gate cap materials while protecting the active area from excessive attack during the cap removal process.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors (NMOS) and/or P-channel transistors (PMOS), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends upon a variety of factors, such as the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on, among other things, the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
When advancing to sophisticated gate architecture based on high-k dielectrics, additionally, transistor performance may also be increased by providing an appropriate conductive material for the gate electrode to replace the typical polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance even at a less critical thickness compared to a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, metal-containing non-polysilicon material, such as titanium nitride and the like, may be formed so as to directly connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Therefore, the threshold voltage of the transistors is significantly affected by the work function of the gate material that is in contact with the gate dielectric material, and an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed. For example, appropriate metal-containing gate electrode materials, such as titanium nitride and the like, may frequently be used in combination with appropriate metal species, such as lanthanum, aluminum and the like, so as to adjust the work function to be appropriate for each type of transistor, i.e., N-channel transistors and P-channel transistors, which may require an additional band gap offset for the P-channel transistor. Given that the gate length on modern transistor devices may be approximately 30-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NMOS transistors and create a compressive stress in the channel region for PMOS transistors). Stress engineering techniques typically involve the formation of specifically made silicon nitride layers that are selectively formed above appropriate transistors, i.e., a layer of silicon nitride that is intended to impart a tensile stress in the channel region of a device would only be formed above the NMOS transistors. Such selective formation may be accomplished by masking the PMOS transistors and then blanket depositing the layer of silicon nitride, or by initially blanket depositing the layer of silicon nitride across the entire substrate and then performing an etching process to selectively remove the silicon nitride from the PMOS transistors. The techniques employed in forming such nitride layers for selective channel stress engineering purposes are well known to those skilled in the art.
Typically, one or more sidewall spacers are formed proximate the gate electrode structures of transistors for a variety of reasons, such as to protect the gate electrode materials, to insure that subsequent structures, such a metal silicide regions formed on the source and drain regions of a transistor, are formed a minimum distance away from the channel region of the device, etc. There is also, typically, a protective cap layer of silicon nitride formed on top of a polysilicon gate electrode (perhaps in combination with an underlying metal layer). This protective cap layer is needed to protect the gate electrode in some processing operations that are performed after the gate electrode is formed, like the formation of cavities in substrate of a PMOS transistor that will be filled with an epitaxial silicon-germanium material, or during processes used to form sidewall spacers. Ultimately, metal silicide regions are typically formed on the source/drain regions and the gate electrode of a transistor to reduce contact resistance. This requires that the protective cap layer be removed from the polysilicon gate structures so that a metal silicide region may be formed on the gate electrode. Typically, the protective cap layer on the gate electrode is removed by performing a reactive ion etching process. However, this etching process damages or recesses the substrate, particularly the epitaxial silicon-germanium regions of the PMOS transistors, and may reduce the thickness of the protective sidewall spacers which are also typically made of silicon nitride (the same material as the protective cap layer). Excessive erosion of the protective sidewall spacers can result in unacceptable shifts in the threshold voltage of the resulting transistors and/or increased yield loss to degradation of the gate electrode structure, e.g., a high-k/metal gate stack.
Some attempts have been made to address this issue. In one technique, a protective liner, e.g., silicon dioxide, may be formed on the gate electrode prior to the formation of the protective cap layer made of silicon nitride. The protective liner may be removed after the protective cap layer above the gate electrode is removed. However, during the etch process that is performed to remove the protective liner, there is a loss of material in the field oxide regions and the overall topology of the device may be adversely affected, which can adversely impact further processing operations, like the creation of more voids in various dielectric layers that will be formed above the device.
Another technique that has been tried involves the formation of a sacrificial fill material between adjacent gate electrode structures and perform a back etch on the fill material to expose the protective cap layer on the gate electrode. A reactive ion etching process is then performed to remove the protective cap layer while the fill material protects the substrate and the sidewall spacers during this etching process. This techniques suffers from poor consistency or homogeneity because the characteristics of the fill formation process and the etching of the protective cap layer on the gate electrode are dependent, to some degree, on the pattern density of the gate electrode structures, which can vary greatly across a typical integrated circuit device, even ignoring manufacturing errors in patterning the gate electrode structures.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.